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Controlador de Comunicación FB3050-TQ

The FB3050 Fieldbus Interface and Controller conforms to the IEC 1158-2 standard, Fieldbus Physical Layer Definition. It provides a high level Master or Slave Fieldbus interface with both embedded and host microprocessors.
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CONTROLADOR DE COMUNICACION FB3050-TQ

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APLICACION MODELO TECNOLOGIA MARCA
Electrónica FB3050-TQ FOUNDATION/ PROFIBUS Smar
FUNCION CODIGO SECCION
Controlador de Comunicación FB3050-TQ 05-2003 05

Fieldbus Communications Controller FB3050 DataSheet
Asynchronous Bus (READY Methodology).

The FB3050 Fieldbus Interface and Controller conforms to the IEC 1158-2 standard, Fieldbus Physical Layer Definition. It provides a high level Master or Slave Fieldbus interface with both embedded and host microprocessors.

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Features
 

  • Built-in Manchester encoder/decoder
  • Built-in two channel DMA controller
  • Automatic polarity detection and correction
  • Automatic receiver frame check sequence (FCS) detection
  • Software controlled transmitter FCS generation
  • Automatic message type and address recognition
  • 31.25K and 1Mbit/sec. data rates
  • Transmitter jabber inhibit circuitry
  • Available in a 100-pin TQFP package
  • Maskable multisource Interrupt Structures reduce software response times
  • CMOS low power consumption and standby mode
  • TIMERS available for data link layer timing
  • Conforms to the ISA SP50 .02 1992 Part 2, Foundation Fieldbus Physical Layer Definition
  • Compatible with all popular microprocessors and microcontrollers
  • Compatible with Motorola and Intel buses



General Description


The FB3050 Fieldbus Interface and Controller conforms to the IEC 1158-2 standard, Fieldbus Physical Layer Definition. It provides a high level Master or Slave Fieldbus interface with both embedded and host microprocessors.

The FB3050 contains Manchester data encoders and decoders on chip and uses a medium interface plus external filters to connect to a Fieldbus system. It automatically detects and corrects polarity reversals on improperly wired connections. The Controller automatically checks the Frame Check Sequence (FCS) for received data packets and generates them for transmitted data packets when enabled by a software control command. Frame status is available by reading the internal status registers. A Jabber Inhibit function helps assure a transmitter does not disable the communications network by transmitting beyond a specified time.

An on-chip two channel Direct Memory Access (DMA) circuit is incorporated for high throughput. Once the DMA is configured, data blocks (frames, buffers) can be sent and received to and from the system memory without significant byte transfer overhead. When interfacing with Intel or generic type processors the DMA uses the READY signal to force the microprocessor into wait status until the DMA access cycle has finished.

Complete control and status information is available through internal registers. These registers are easily read or written to configure and operate the FB3050 Controller. To facilitate interfacing with various host controllers, two clock sources are used; one for system synchronization and a second for data rate control.

To reduce software overhead, the FB3050 Controller provides detection of the Frame Control character. Depending on the value received, an equality test for 8 bit, 16 bit or 32 bit addresses is made by comparing the received address with a table of addresses contained in memory. The search for a match is automatic. An interrupt is generated when a match occurs. Only one address loads into an internal register for an 8 bit compare. Address fields in memory support a variable number of 16 bit and 32 bit addresses. Frame Control message types that do not require address recognition are also detected and can generate an interrupt.

The FB3050 has a flexible interrupt structure. A single interrupt will cause the host to read internal status registers to determine the source. All interrupt sources are maskable and identifiable. An interrupt is generated by a number of conditions or by any of the controllers’ three timers. The Timer Module provides octet, 1/32 millisecond and millisecond timing references. All of these conditions are also maskable.

 








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