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Controlador de Comunicación FB4050-TQ

The FB4050 Fieldbus Interface and Controller conforms to the IEC 1158- 2 standard, Fieldbus Physical Layer Definition. It provides a high level Master or Slave Fieldbus interface with both embedded and host microprocessors.
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CONTROLADOR DE COMUNICACION FB4050-TQ

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APLICACION MODELO TECNOLOGIA MARCA
Electrónica FB4050-TQ FOUNDATION/ PROFIBUS Smar
FUNCION CODIGO SECCION
Controlador de Comunicación FB4050-TQ 05-2002 05

Fieldbus Communications Controller FB4050 DataSheet
Asynchronous Bus (READY Methodology).

The FB4050 Fieldbus Interface and Controller conforms to the IEC 1158- 2 standard, Fieldbus Physical Layer Definition. It provides a high level Master or Slave Fieldbus interface with both embedded and host microprocessors.

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Features

  • Software controlled transmitter FCS generation
  • Transmitter jabber inhibit circuitry
  • Maskable Multisource Interrupt Structures reduce software response times
  • Timers available for Data Link Layer timing
     
  • Built-in:
  • Floating Point Coprocessor Unit (FPU) increases processing performance
  • Manchester encoder/decoder
  • two channel DMA controller
  • LCD driver for up to a 160-segment display
     
  • Automatic :
  • LCD Position Orientation and Segment Reorganization allows multiple display positions
  • polarity detection and correction
  • receiver frame check sequence (FCS) detection
  • message type and address recognition
     
  • Simplifies design, shortens development schedule, saves on parts and lowers cost of manufacturing
  • Conforms to Fieldbus H1 Device standards and Profibus PA
  • Designed for easy integration with Mitsubishi M16 and Intel 80186/80188 microprocessors


General Description


The FB4050 Fieldbus Interface and Controller conforms to the IEC 1158- 2 standard, Fieldbus Physical Layer Definition. It provides a high level Master or Slave Fieldbus interface with both embedded and host microprocessors.

The FB4050 contains Manchester data encoders and decoders on chip. Only a medium interface and external filters are needed to connect to a Fieldbus system. The FB4050 automatically detects and corrects polarity reversals on improperly wired connections, automatically checks the Frame Check Sequence (FCS) for received data packets, and generates FCS for transmitted data packets when enabled by a software control command.

Frame status is available by software control commands in internal status registers. A Jabber Inhibit function helps assure a transmitter does not disable the communications network by transmitting beyond a specified time.

To accommodate high throughput, the FB4050 Controller features an onchip two-channel Direct Memory Access (DMA) circuit. When the DMA is configured, data blocks (frames, buffers) can be sent and received to and from the system memory without significant byte transfer overhead. When interfacing to the microprocessor, the FB4050 uses the PO_HOLD signal to request the microprocessor to go into a wait state and the microprocessor uses the PI_HLDA signal to acknowledge the request until the DMA access cycle has finished. When the FB4050 has finished its DMA cycle, the PO_HOLD signal will return to its inactive state (high) and the CPU will return PI_HLDA to its inactive state. In the cases where multiple FB4050’s are used in the same device, the PO_HOLD signals can share the same signal path to the CPU. However, the PO_HLDA signal from the previous FB4050 must be connected to the PI_HLDA of the next FB4050. This effectively forms a “daisychain” that will pass along the signal to each controller.

In-the-field readable output is achieved with an integrated three-ledger 160-segment display driver. This LCD driver can be used to output device readings and calculations to various types of LCD’s in the field. The display frequency can be modified by software control commands to various divisions of the input clock frequency. The display module has the added capability of detecting the LCD position and reorganizing the data segments appropriately to accommodate for various LCD rotations suited to each device location.

A 32-bit floating point unit is also incorporated into the FB4050.This FPU can perform the following operations:

  • Addition
  • Subtraction
  • Multiplication
  • Division
  • float to integer conversion
  • integer to float conversion
  • Clear contents of accumulator A.


The inclusion of the FPU in the FB4050 improves performance by allowing the microprocessor to execute other tasks while the FB4050 performs the floating point calculations. The FPU operation frequency can be modified by software control commands to various divisions of the input clock frequency.

To reduce software overhead, the FB4050 Controller provides detection of the Frame Control character. Depending on the value received a test for equality for 8 bit, 16 bit or 32 bit addresses is made by comparing the received address with a table of addresses contained in memory. The search for a match is automatic. An interrupt is generated when a match occurs. Only one address loads into an internal register(fb_nodeid) for an 8 bit compare. Address fields in memory support a variable number of 16 bit and 32 bit addresses. Frame Control message types that do not require address recognition are also detected and can generate an interrupt.

The FB4050 has a flexible interrupt structure. A single interrupt will cause the host to read internal status registers to determine the source. All interrupt sources are maskable and identifiable. An interrupt is generated by a number of conditions or by any of the controllers’ three timers. The Timer Module provides octet, 1/32 millisecond and millisecond timing references. All of these conditions are also maskable. When only one FB4050 is used in the device, the PI_INTR pin is connected directly to the CPU to monitor external interrupts. In the cases where multiple FB4050’s are used in the same device, the PO_INTR signal from the previous FB4050 must be connected to the PI_INTR of the next FB4050. This effectively forms a “daisychain” that will pass along the signal to each controller. The PO_INTR and PI_INTR signals are active level low, effectively being active for the entire duration the signal is low and not just on the falling edge. Because of this, it is required to manually reset the interrupt after the interrupt service routine is completed; otherwise the service routine will run indefinitely.








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